Display device and method of manufacturing same

ABSTRACT

A display device includes a substrate including a first area, a second area, and a bent area therebetween, an inner wiring disposed in the first area, an outer wiring disposed in the second area, an inter-insulating layer which covers the inner wiring and the outer wiring and in which an opening corresponding to the bent area is defined, a first organic insulating layer, where a portion thereof is located in the opening, a connection wiring disposed on the first organic insulating layer and connecting the inner wiring to the outer wiring, a conductive layer disposed between the inter-insulating layer and the first organic insulating layer and electrically connected to one of the inner wiring and the outer wiring, and an inorganic protective layer which covers the conductive layer and in which an opening corresponding to the bent area is defined.

This application is a continuation of U.S. patent application Ser. No.16/876,483, filed on May 18, 2020, which is a continuation of U.S.patent application Ser. No. 16/056,899, filed on Aug. 7, 2018, whichclaims priority to Korean Patent Application No. 10-2017-0163690, filedon Nov. 30, 2017, and all the benefits accruing therefrom under 35U.S.C. § 119, the content of which in its entirety is hereinincorporated by reference.

BACKGROUND 1. Field

One or more exemplary embodiments relate to a display device and amethod of manufacturing the same.

2. Description of the Related Art

Recently, usages of a display device have become more diversified. Also,as the display device becomes thinner and more lightweight, a range ofthe uses of the display device has been gradually extended. As thedisplay device is utilized in various ways, a design of the displaydevice, such as an ability to bend at least a portion of the displaydevice, has been diversified.

SUMMARY

To bend a display device, a structure and a process for preventingoccurrence of a crack, etc., around a bent area are desired, and thusthe structure may be complicated and a number of processes may furtherincrease compared with a display device not including a bendable area.

One or more exemplary embodiments include a display device desiring aminimum process and including a bent area having a structurecorresponding thereto. However, this objective is provided as an exampleand the scope of the invention is not limited thereto.

Additional exemplary embodiments will be set forth in part in thedescription which follows and, in part, will be apparent from thedescription, or may be learned by practice of the presented embodiments.

According to one or more exemplary embodiments, a display deviceincludes a substrate including a first area, a second area, and a bentarea between the first and second areas, an inner wiring disposed in thefirst area, an outer wiring disposed in the second area, aninter-insulating layer which covers the inner wiring and the outerwiring and in which an opening corresponding to the bent area isdefined, a first organic insulating layer, a portion of the firstorganic insulating layer being located in the opening, a connectionwiring disposed on the first organic insulating layer and connecting theinner wiring and the outer wiring, a conductive layer disposed betweenthe inter-insulating layer and the first organic insulating layer andelectrically connected to one of the inner wiring and the outer wiring,and an inorganic protective layer which covers the conductive layer andin which an opening corresponding to the bent area is defined.

In an exemplary embodiment, an upper surface of an end portion of theinter-insulating layer which is adjacent to the opening of theinter-insulating layer may be covered by the inorganic protective layer.

In an exemplary embodiment, the display device may further include alower insulating layer, the lower insulating layer being disposed belowthe inner wiring such that the inner wiring is located between the lowerinsulating layer and the inter-insulating layer, and the lowerinsulating layer in which an opening corresponding to the bent area isdefined.

In an exemplary embodiment, the lower insulating layer and theinter-insulating layer may form a step difference in a region adjacentto the bent area.

In an exemplary embodiment, an end portion of the inorganic protectivelayer may cover a lateral surface of the inter-insulating layer and anupper surface of the lower insulating layer in a region adjacent to thebent area.

In an exemplary embodiment, an end portion of the inorganic protectivelayer may be covered by the first organic insulating layer in a regionadjacent to the bent area.

In an exemplary embodiment, the first organic insulating layer maydirectly contact the substrate in the bent area.

In an exemplary embodiment, the substrate may include a base layer andan inorganic barrier layer which is disposed on the base layer and inwhich an opening corresponding to the bent area is defined, and thefirst organic insulating layer directly contacting the base layer.

In an exemplary embodiment, the first area may include a display areaincluding a plurality of pixels, and each pixel may include a thin filmtransistor, a pixel electrode electrically connected to the thin filmtransistor, an opposite electrode facing the pixel electrode, and anintermediate layer between the pixel electrode and the oppositeelectrode, the intermediate layer including an emission layer.

In an exemplary embodiment, the display device may further include asecond organic insulating layer disposed between the connection wiringand the pixel electrode.

According to one or more exemplary embodiments, a display deviceincludes a display area including a thin film transistor on a substrate,and a display element including a pixel electrode, an intermediatelayer, and an opposite electrode sequentially stacked, a non-displayarea adjacent to the display area and including a bent area, an innerwiring and an outer wiring mutually spaced apart from each other withthe bent area therebetween, an inter-insulating layer which is disposedon the inner wiring and the outer wiring and in which an openingcorresponding to the bent area is defined, a connection wiringelectrically connecting the inner wiring to the outer wiring and passingacross the bent area, and a first organic insulating layer disposed inthe display area and the non-display area, a portion of the firstorganic insulating layer being located in the opening of theinter-insulating layer, where the connection wiring is disposed belowthe pixel electrode with an insulating layer therebetween.

In an exemplary embodiment, the display device may further include aconductive layer disposed between the inner wiring and the connectionwiring, and between the outer wiring and the connection wiring.

In an exemplary embodiment, the display device may further include aninorganic protective layer which is disposed on the conductive layer andin which an opening corresponding to the bent area is defined.

In an exemplary embodiment, an end portion of the inorganic protectivelayer may cover the inter-insulating layer and may be covered by thefirst organic insulating layer in a region adjacent to the bent area.

In an exemplary embodiment, the display device may further include alower insulating layer which is disposed below the inner wiring suchthat the inner wiring is located between the lower insulating layer andthe inter-insulating layer and in which an opening corresponding to thebent area is defined.

In an exemplary embodiment, the substrate may include a base layer andan inorganic barrier layer on the base layer, the lower insulating layerbeing the inorganic barrier layer.

In an exemplary embodiment, the first organic insulating layer maydirectly contact the base layer of the substrate.

In an exemplary embodiment, the inter-insulating layer and the lowerinsulating layer may form a step difference.

In an exemplary embodiment, a width of the opening of the lowerinsulating layer may be greater than a width of the bent area.

In an exemplary embodiment, a width of the opening of theinter-insulating layer may be greater than a width of the opening of thelower insulating layer.

According to one or more exemplary embodiments, a method ofmanufacturing a display device includes forming a thin film transistorand a storage capacitor in a display area, forming an inner wiring andan outer wiring in a non-display area, the inner wiring and the outerwiring being spaced apart from each other around a bent area, forming aninter-insulating layer which is disposed on the inner wiring and theouter wiring, and in which an opening corresponding to the bent area isdefined, forming a connection metal connected to the thin filmtransistor, forming a conductive layer connected to the inner wiring andthe outer wiring, forming an inorganic protective layer covering theconnection metal and the conductive layer, and etching the inorganicprotective layer to define a hole exposing the connection metal, a firstcontact hole exposing the conductive layer, and an opening correspondingto the bent area, where the etching of the inorganic protective layerincludes etching at least one lower inorganic insulating layer providedbelow the inorganic protective layer such that an opening correspondingto the bent area is defined in the at least one lower inorganicinsulating layer.

In an exemplary embodiment, the etching of the inorganic protectivelayer and the etching of the at least one lower inorganic insulatinglayer may be performed during a same mask process using a halftone mask.

In an exemplary embodiment, an end portion of the inter-insulating layerand an end portion of the at least one lower inorganic insulating layermay form a step difference in a region adjacent to the bent area.

In an exemplary embodiment, an end portion of the inorganic protectivelayer may be located on an end portion of the inter-insulating layer ina region adjacent to the bent area.

In an exemplary embodiment, an end portion of the inorganic protectivelayer may be located on an end portion of the at least one lowerinorganic insulating layer in a region adjacent to the bent area.

In an exemplary embodiment, the method may further include forming afirst organic insulating layer on the inorganic protective layer suchthat a portion of the first organic insulating layer is located in theopening of the inter-insulating layer and the opening of the at leastone lower inorganic insulating layer.

In an exemplary embodiment, the first organic insulating layer mayextend to the display area such that the first organic insulating layeris disposed on the connection metal.

In an exemplary embodiment, a second contact hole exposing theconductive layer may be defined in the first organic insulating layer,and the method may further include forming a connection wiring connectedto the conductive layer through the second contact hole.

In an exemplary embodiment, the method may further include forming asecond organic insulating layer on the connection wiring, and forming apixel electrode on the second organic insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other exemplary embodiments will become apparent and morereadily appreciated from the following description of the exemplaryembodiments, taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a plan view of a display device according to an exemplaryembodiment;

FIG. 2 is a perspective view of a portion of a display device accordingto an exemplary embodiment;

FIG. 3 is a cross-sectional view of a display device according to anexemplary embodiment;

FIG. 4A is an enlarged cross-sectional view of a partial region around abent area of FIG. 3;

FIG. 4B is a view of a modification of FIG. 4A;

FIG. 5 is a cross-sectional view of a display device according toanother exemplary embodiment and corresponding to cross-sections of thedisplay device taken along lines A-A′ and B-B′ of FIG. 1;

FIG. 6 is a plan view of a portion of a wiring unit of a display deviceaccording to an exemplary embodiment;

FIG. 7 is a cross-sectional view of the wiring unit taken along lineVII-VII′ of FIG. 6;

FIG. 8 is a cross-sectional view of the wiring unit taken along lineVIII-VIII′ of FIG. 6;

FIG. 9 is a cross-sectional view of the wiring unit taken along lineIX-IX′ of FIG. 6;

FIG. 10 is a cross-sectional view of a display device according toanother exemplary embodiment;

FIG. 11A is an enlarged cross-sectional view of a portion of a displaydevice around a bent area of FIG. 10, according to another exemplaryembodiment;

FIG. 11B is a view of a modification of FIG. 11A;

FIG. 12 is a cross-sectional view of a display device according toanother exemplary embodiment;

FIGS. 13A to 13G are cross-sectional views of a method of manufacturinga display device, according to an exemplary embodiment; and

FIG. 14 is a cross-sectional view of a sixth mask process of a method ofmanufacturing a display device, according to another exemplaryembodiment.

DETAILED DESCRIPTION

As the invention allows for various changes and numerous embodiments,exemplary embodiments will be illustrated in the drawings and describedin detail in the written description. Effects and characteristics ofexemplary embodiments, and a method of accomplishing them will beapparent by referring to content described below in detail together withthe drawings. However, the exemplary embodiments are not limited toexemplary embodiments below and may be implemented in various forms.

Hereinafter, embodiments of the invention are described in detail withreference to the accompanying drawings, and when descriptions are madewith reference to the drawings, like or corresponding elements are givenlike reference numerals and repeated descriptions thereof are omitted.

It will be understood that although the terms “first”, “second”, etc.,may be used herein to describe various components, these componentsshould not be limited by these terms. These components are only used todistinguish one component from another.

As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise.

It will be further understood that the terms “comprises/includes” and/or“comprising/including” used herein specify the presence of statedfeatures or components, but do not preclude the presence or addition ofone or more other features or components.

It will be understood that when a layer, region, or component isreferred to as being “disposed on” another layer, region, or component,it can be directly or indirectly disposed on the other layer, region, orcomponent. That is, for example, intervening layers, regions, orcomponents may be present.

Sizes of elements in the drawings may be exaggerated for convenience ofexplanation. In other words, since sizes and thicknesses of componentsin the drawings are arbitrarily illustrated for convenience ofexplanation, the following embodiments are not limited thereto.

“About” or “approximately” as used herein is inclusive of the statedvalue and means within an acceptable range of deviation for theparticular value as determined by one of ordinary skill in the art,considering the measurement in question and the error associated withmeasurement of the particular quantity (i.e., the limitations of themeasurement system). For example, “about” can mean within one or morestandard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

When a certain embodiment may be implemented differently, a specificprocess order may be performed differently from the described order. Forexample, two consecutively described processes may be performedsubstantially at the same time or performed in an order opposite to thedescribed order.

It will be understood that when a layer, region, or component isreferred to as being “connected” to another layer, region, or component,it may be “directly connected” to the other layer, region, or componentor may be “indirectly connected” to the other layer, region, orcomponent with other layer, region, or component interposedtherebetween. For example, it will be understood that when a layer,region, or component is referred to as being “electrically connected” toanother layer, region, or component, it may be “directly electricallyconnected” to the other layer, region, or component or may be“indirectly electrically connected” to other layer, region, or componentwith other layer, region, or component interposed therebetween.

In the following examples, the x-axis, the y-axis and the z-axis are notlimited to three axes of the rectangular coordinate system, and may beinterpreted in a broader sense. For example, the x-axis, the y-axis, andthe z-axis may be perpendicular to one another, or may representdifferent directions that are not perpendicular to one another.

A display device is an apparatus displaying an image and may be a liquidcrystal display, an electrophoretic display, an organic light-emittingdisplay, an inorganic light-emitting display, a field emission display,a surface-conduction electron-emitter display, a plasma display, acathode ray display, etc.

Exemplary embodiments of the invention may prevent a damage of a bentarea through a relatively simple structure, and improve a manufacturingefficiency by reducing a mask process. However, the scope of theinvention is not limited by this effect, and this effect is provided asan example and effects corresponding to embodiments are described indetail through contents below.

Hereinafter, though an organic light-emitting display as a displaydevice according to an exemplary embodiment is described as an example,the display device is not limited thereto and various types of displaydevices may be used.

FIG. 1 is a plan view of a display device according to an exemplaryembodiment, and FIG. 2 is a perspective view of a portion of a displaydevice according to an exemplary embodiment.

Referring to FIGS. 1 and 2, the substrate 100 may have a bent area BAextending in a first direction (e.g., Y direction). The bent area BA maybe located between a first area 1A and a second area 2A in a seconddirection (e.g., X direction) crossing the first direction.

The substrate 100 may be bent around a bending axis BAX extending in thefirst direction. Although FIG. 2 illustrates that the substrate 100 isbent at the same curvature radius around the bending axis BAX, theinvention is not limited thereto. The substrate 100 may be bent aroundthe bending axis BAX and a curvature radius thereof may not be constant.

In an exemplary embodiment, the substrate 100 may include variousflexible or bendable materials, for example, may include polymer resinssuch as polyethersulphone (“PES”), polyacrylate (“PAR”), polyetherimide(“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate(“PET”), polyphenylene sulfide (“PPS”), polyarylate, polyimide (“PI”),polycarbonate (“PC”), or cellulose acetate propionate (“CAP”).

The first area 1A may include a display area DA. As illustrated in FIG.1, the first area 1A may include the display area DA and a portion of anon-display area NDA outside the display area DA. The second area 2A andthe bent area BA may include the non-display area NDA. The display areaDA of the display device may correspond to a portion of the first area1A, and the non-display area NDA may correspond to the rest of the firstarea 1A, the second area 2A, and the bent area BA.

The display area DA may include pixels P and display an image. A pixel Pmay be connected to signal lines such as a scan line SL extending in thefirst direction and a data line DL extending in the second direction.Though not shown in FIG. 1, the pixel P may be connected to power linestransferring a current signal such as a driving power line and a commonpower line. In an exemplary embodiment, the current signal of thedriving power line and the common power line may be a direct current(“DC”) voltage, for example, but the invention is not limited thereto.

The pixel P may include electronic elements such as a thin filmtransistor (“TFT”) and a storage capacitor electrically connected to theabove-described signal lines and power lines, and an organiclight-emitting device (“OLED”) connected to the above-describedelectronic elements. The pixel P may emit, for example, red, green,blue, or white light through an OLED. A pixel in the specification maybe understood as a pixel emitting light of one of red, green, and blue,or a pixel emitting light of one of red, green, blue, and white asdescribed above. However, the invention is not limited thereto, and thepixel may emit light having various other colors. The display area DAmay be covered by an encapsulation layer 400 and thereby protected fromexternal air or moisture. In the case where a display element providedto the pixel P is an OLED, the TFTs may include a driving TFT and aswitching TFT, and may further include an additional TFT in addition tothe above-described two TFTs depending on the design of the pixel P.

The non-display area NDA may include first and second scan drivers 11and 12, a terminal unit 20, a driving voltage supply line 30, a commonvoltage supply line 40, and a wiring unit 50.

The first and second scan drivers 11 and 12 may be disposed in the firstarea 1A. In an exemplary embodiment, the first and second scan drivers11 and 12 may be spaced apart from each other with the display area DAtherebetween, for example. The first and second scan drivers 11 and 12may generate a scan signal and transfer the scan signal to each pixel Pthrough a scan line SL. Although FIG. 1 illustrates a case where the twoscan drivers are disposed, the invention is not limited thereto. Inanother exemplary embodiment, one scan driver may be disposed on oneside of the display area DA.

The terminal unit 20 may be disposed on one end portion of thenon-display area NDA, and may include terminals 21, 22, 23, and 24. Theterminal unit 20 may be exposed without being covered by an insulatinglayer and connected to a flexible film 60 such as a flexible printedcircuit board including a driver integrated circuit (“IC”) 70. AlthoughFIG. 1 illustrates a chip on film (“COF”) type IC in which the driver IC70 is connected through the flexible film 60, the invention is notlimited thereto. In another exemplary embodiment, the driver IC 70 maybe a chip on panel (“COP”) type IC in which the driver IC 70 is disposed(e.g. directly disposed) on the terminal unit 20 of the substrate 100.

The driving voltage supply line 30 may provide a driving voltage to thepixels P. The driving voltage supply line 30 may be disposed in thenon-display area NDA such that the driving voltage supply line 30 isadjacent to one side of the display area DA.

The common voltage supply line 40 may provide a common voltage to thepixels P. The common voltage supply line 40 may be disposed in thenon-display area NDA to partially surround the display area DA.

The wiring unit 50 may include inner wirings 210 disposed in the firstarea 1A, outer wirings 220 disposed in the second area 2A, andconnection wirings 240 which are bridge wirings electrically connectingthe inner wirings 210 to the outer wirings 220. Each inner wiring 210may be electrically connected to a signal line of the display area DA,and each outer wiring 220 may be electrically connected to the terminalunit 20 of the non-display area NDA.

The connection wiring 240 may extend from the first area 1A to thesecond area 2A across the bent area BA. The connection wiring 240 maycross the bending axis BAX described with reference to FIG. 2. Althoughthe connection wiring 240, which is a bridge wiring, extendsperpendicularly with respect to the bending axis BAX in FIG. 1, theinvention is not limited thereto. The connection wiring 240 mayobliquely extend such that the connection wiring 240 has a preset anglewith respect to the bending axis BAX, or may extend while having variousshapes such as a curved shape and a zigzag shape, not a straight lineshape.

FIG. 3 is a cross-sectional view of a display device according to anexemplary embodiment and corresponds to cross-sections of the displaydevice taken along lines A-A′ and B-B′ of FIG. 1, FIG. 4A is an enlargedcross-sectional view of a partial region around the bent area BA of FIG.3, and FIG. 4B is a view of a modification of FIG. 4A.

Referring to the cross-section of FIG. 3 taken along line A-A′ of FIG.1, an OLED 300 as a display element may be disposed in the display areaDA. The OLED 300 may be electrically connected to first and second TFTsT1 and T2, and a storage capacitor Cst. The first TFT T1 includes afirst semiconductor layer Act1 and a first gate electrode G1, and thesecond TFT T2 includes a second semiconductor layer Act2 and a secondgate electrode G2.

The first semiconductor layer Act1 and the second semiconductor layerAct2 may include amorphous silicon, polycrystalline silicon, an oxidesemiconductor, or an organic semiconductor material. The firstsemiconductor layer Act1 may include a channel region C1, and a sourceregion S1 and a drain region D1 respectively disposed at opposite sidesof the channel region C1. The second semiconductor layer Act2 mayinclude a channel region C2, and a source region S2 and a drain regionD2 respectively disposed at opposite sides of the channel region C2. Thefirst and second source regions S1 and S2, and the first and seconddrain regions D1 and D2 respectively of the first and secondsemiconductor layers Act1 and Act2 may be understood as sourceelectrodes and drain electrodes respectively of the first and secondTFTs T1 and T2.

The first gate electrode G1 and the second gate electrode G2 mayrespectively overlap the channel region C1 of the first semiconductorlayer Act1 and the channel region C2 of the second semiconductor layerAct2 with a gate insulating layer 120 therebetween. In an exemplaryembodiment, the first and second gate electrodes G1 and G2 may include asingle layer or a multi-layer including a conductive material includingat least one of Mo, Al, Cu, and Ti, for example. Although FIG. 3illustrates that the first gate electrode G1 and the second gateelectrode G2 are disposed in the same layer, the invention is notlimited thereto. In another exemplary embodiment, the first gateelectrode G1 and the second gate electrode G2 may be respectivelydisposed in different layers.

Although FIG. 3 illustrates a top-gate type TFT in which the first andsecond gate electrodes G1 and G2 are respectively disposed over thefirst and second semiconductor layers Act1 and Act2, the invention isnot limited thereto. In another exemplary embodiment, the TFT may be abottom-gate type TFT in which the first and second gate electrodes G1and G2 are respectively disposed below the first and secondsemiconductor layers Act1 and Act2.

The storage capacitor Cst may include a first storage capacitor plateCE1 and a second storage capacitor plate CE2 overlapping each other. Inan exemplary embodiment, the first and second storage capacitor platesCE1 and CE2 may include a low-resistance conductive material includingat least one of Mo, Al, Cu, and Ti, for example.

The storage capacitor Cst may overlap the first TFT T1, and the firstTFT T1 may be a driving TFT. Although FIG. 3 illustrates a case wherethe storage capacitor Cst overlaps the first TFT T1 and thereby thefirst storage capacitor plate CE1 serves as the first gate electrode G1of the first TFT T1, the invention is not limited thereto. In anotherexemplary embodiment, the storage capacitor Cst may not overlap thefirst TFT T1.

A buffer layer 110 may be disposed between the substrate 100 and thefirst and second TFTs T1 and T2. The buffer layer 110 may include aninorganic insulating layer. In an exemplary embodiment, the buffer layer110 may include a single layer or a multi-layer including at least oneof SiON, SiOx, and SiNx, for example.

The gate insulating layer 120 may be disposed between the first andsecond gate electrodes G1 and G2 and the first and second semiconductorlayers Act1 and Act2. The gate insulating layer 120 may include aninorganic insulating layer. In an exemplary embodiment, the gateinsulating layer 120 may include a single layer or a multi-layerincluding at least one of SiON, SiOx, and SiNx, for example.

The first and second TFTs T1 and T2 may be covered by aninter-insulating layer 130. FIG. 3 illustrates that the inter-insulatinglayer 130 includes first and second inter-insulating layers 131 and 132.The first inter-insulating layer 131 may be disposed directly on thefirst and second TFTs T1 and T2 and/or directly on the first storagecapacitor plate CE1. The second inter-insulating layer 132 may bedisposed on the second storage capacitor plate CE2. The first and secondinter-insulating layers 131 and 132 may include an inorganic insulatingmaterial. In an exemplary embodiment, each of the first and secondinter-insulating layers 131 and 132 may include a single layer or amulti-layer including at least one of SiON, SiOx, and SiNx, for example.In an exemplary embodiment, the first inter-insulating layer 131 mayinclude a single layer including SiNx, and the second inter-insulatinglayer 132 may include a multi-layer including SiNx and SiOx, forexample. In the specification, the inter-insulating layer may beunderstood as an insulating layer between the inner wiring 210 and aconductive layer 230 and/or between the outer wiring 220 and theconductive layer 230 in the non-display area NDA and understood asrepresenting the first inter-insulating layer 131, representing thesecond inter-insulating layer 132, or representing the first and secondinter-insulating layers 131 and 132.

A data line DL may be disposed on the inter-insulating layer 130. Thedata line DL may be electrically connected to a switching TFT (notshown) to provide a data signal. In an exemplary embodiment, the dataline DL may include a single layer or a multi-layer including at leastone of Al, Cu, Ti, and an alloy thereof, for example. In an exemplaryembodiment, the data line DL may include a three-story layer ofTi/Al/Ti, for example.

The data line DL may be covered by an inorganic protective layer PVX. Inan exemplary embodiment, the inorganic protective layer PVX may be aninorganic insulating layer and may include a single layer or amulti-layer including SiNx and SiOx, for example. Though not shown, theinorganic protective layer PVX may cover and protect some wiringsexposed in the non-display area NDA. Wirings (not shown) simultaneouslyprovided during the same process as a process of the data line DL may beexposed to a portion of the substrate 100 (for example, a portion of thenon-display area NDA). An exposed portion of the wirings may be damagedby an etchant used when a pixel electrode 310, which will be describedlater, is patterned. However, according to the exemplary embodiment,since the inorganic protective layer PVX covers the data line DL and atleast some of the wirings simultaneously provided with the data line DL,the wirings may be prevented from being damaged during a patterningprocess of the pixel electrode 310.

The driving voltage line PL may be disposed in a layer different from alayer in which the data line DL is disposed. In the specification, itwill be understood that when “A and B are disposed in different layers”,at least one insulating layer is disposed between A and B, and therebyat least one of A and B is disposed below the at least one insulatinglayer and the other is disposed over the at least one insulating layer.A first organic insulating layer 141 may be disposed between the drivingvoltage line PL and the data line DL. In an exemplary embodiment, thefirst organic insulating layer 141 is a planarization layer and mayinclude a general-purpose polymer such as an imide-based polymer,polymethylmethacrylate (“PMMA”) or polystyrene (“PS”), or polymerderivatives having a phenol-based group, an acryl-based polymer, an arylether-based polymer, an amide-based polymer, a fluorine-based polymer, ap-xylene-based polymer, a vinyl alcohol-based polymer, or anycombinations thereof.

In an exemplary embodiment, the driving voltage line PL may include asingle layer or a multi-layer including at least one of Al, Cu, Ti, andan alloy thereof, for example. In an exemplary embodiment, the drivingvoltage line PL may include a three-story layer of Ti/Al/Ti, forexample. Although FIG. 3 illustrates a configuration in which thedriving voltage line PL is disposed on only the first organic insulatinglayer 141, the invention is not limited thereto. In another exemplaryembodiment, the driving voltage line PL may be connected to anadditional lower voltage line (not shown) simultaneously provided withthe data line DL through a through hole (not shown) defined in the firstorganic insulating layer 141 to reduce a resistance.

A second organic insulating layer 142 may cover the driving voltage linePL. In an exemplary embodiment, the second organic insulating layer 142is a planarization layer and may include a general-purpose polymer suchas an imide-based polymer, PMMA or PS, or polymer derivatives having aphenol-based group, an acryl-based polymer, an aryl ether-based polymer,an amide-based polymer, a fluorine-based polymer, a p-xylene-basedpolymer, a vinyl alcohol-based polymer, or any combinations thereof.

The OLED 300 including the pixel electrode 310, an opposite electrode330, and an intermediate layer 320 including an emission layer anddisposed between the pixel electrode 310 and the opposite electrode 330,may be disposed on the second organic insulating layer 142.

A pixel-defining layer 150 may be disposed on the pixel electrode 310.The pixel-defining layer 150 defines a pixel by defining an openingcorresponding to respective sub-pixels, that is, an opening exposing atleast a central portion of the pixel electrode 310. Also, thepixel-defining layer 150 may prevent an arc, etc., from occurringbetween the pixel electrode 310 and the opposite electrode 330 byincreasing a distance between the edge of the pixel electrode 310 andthe opposite electrode 330. In an exemplary embodiment, thepixel-defining layer 150 may include, for example, an organic materialsuch as PI or hexamethyldisiloxane (“HMDSO”).

The pixel electrode 310 may be electrically connected to a pixel circuitincluding, for example, the first and second TFTs T1 and T2 and thestorage capacitor Cst through a first connection metal CM1 and a secondconnection metal CM2.

The intermediate layer 320 may include a low molecular or polymermaterial. In the case where the intermediate layer 320 includes a lowmolecular material, the intermediate layer 320 may have a structure inwhich a hole injection layer (“HIL”), a hole transport layer (“HTL”), anemission layer (“EML”), an electron transport layer (“ETL”), an electroninjection layer (“EIL”), etc., are stacked in a single or a compositeconfiguration, and may include various organic materials such as copperphthalocyanine (CuPc), N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine(“NPB”), and tris-8-hydroxyquinoline aluminum (Alq3). These layers maybe provided by vacuum evaporation.

In the case where the intermediate layer 320 includes a polymermaterial, the intermediate layer 320 may generally have a structureincluding an HTL and an EML. In this case, the HTL may include PEDOT,and the EML may include a polymer material such as polyphenylenevinylene (“PPV”)-based material and a polyfluorene-based material. Thestructure of the intermediate layer 320 is not limited to theabove-described structure and may have various structures. In anexemplary embodiment, the intermediate layer 320 may include a layerhaving one body over a plurality of pixel electrodes 310 or may includea layer patterned to respectively correspond to the plurality of pixelelectrodes 310, for example.

The opposite electrode 330 may cover the display area DA. That is, theopposite electrode 330 may have one body over the plurality of OLEDs300.

Since the OLED 300 may be easily damaged by external moisture or oxygen,the OLED 300 may be protected by being covered by an encapsulation layer400. The encapsulation layer 400 may cover the display area DA andextend to the outside of the display area DA. The encapsulation layer400 includes at least one inorganic insulating layer and at least oneorganic insulating layer. In an exemplary embodiment, the encapsulationlayer 400 may include a first inorganic encapsulation layer 410, anorganic encapsulation layer 420, and a second inorganic encapsulationlayer 430, for example.

In an exemplary embodiment, the first inorganic encapsulation layer 410may cover the opposite electrode 330 and include SiOx, SiNx, and/orSiON, for example. Though not shown, other layers such as a cappinglayer may be disposed between the first inorganic encapsulation layer410 and the opposite electrode 330. Since the first inorganicencapsulation layer 410 is disposed along a structure thereunder, anupper surface of the first inorganic encapsulation layer 410 is notplanarized. The organic encapsulation layer 420 covering the firstinorganic encapsulation layer 410 may have a flat upper surface at leastcorresponding to the display area DA. In an exemplary embodiment, theorganic encapsulation layer 420 may include at least one of PET, PEN,PC, PI, polyethylene sulfonate, polyoxymethylene (“POM”), polyarylate,and HMDSO, for example. In an exemplary embodiment, the second inorganicencapsulation layer 430 may cover the organic encapsulation layer 420and include SiOx, SiNx, and/or SiON, for example.

An optical film 500 may be disposed on the encapsulation layer 400. Theoptical film 500 may include a polarization plate. The polarizationplate may reduce external light reflection, and a layer including ablack matrix and a color filter may be used instead of the polarizationplate. Though not shown, various functional layers including touchelectrode layers may be further provided on the encapsulation layer 400.

Referring to the non-display area NDA of FIG. 3 taken along line B-B′ ofFIG. 1, the buffer layer 110, the gate insulating layer 120, theinter-insulating layer 130, and the inorganic protective layer PVX maybe collectively referred to as inorganic insulating layers IL.

Although FIG. 3 illustrates that a display device is not bent, forconvenience of description, the substrate 100, etc., of the displaydevice according to the invention may be bent in the bent area BA asillustrated in FIG. 2. In an exemplary embodiment, as illustrated inFIG. 3, the display device is manufactured while the substrate 100 isapproximately flat, and after that, the substrate 100 is bent in thebent area BA and may have the shape illustrated in FIG. 2, for example.While the substrate 100, etc., are bent in the bent area BA, tensilestress may be applied to elements disposed inside the bent area BA.

To prevent a crack from occurring in the inorganic insulating layer ILdue to tensile stress, an opening OP corresponding to the bent area BAis defined in the inorganic insulating layer IL. In the specification,“corresponding” may be understood as “overlapping”. Openings 110 a, 120a, 130 a, and PVXa corresponding to the bent area BA may be respectivelydefined in the buffer layer 110, the gate insulating layer 120, theinter-insulating layer 130, and the inorganic protective layer PVX. Theopening 130 a of the inter-insulating layer 130 may include the openings131 a and 132 a respectively of the first and second inter-insulatinglayers 131 and 132. The opening OP of the inorganic insulating layer ILis defined such that the opening OP passes through the inorganicinsulating layer IL as illustrated in FIG. 3.

An area of the opening OP may be wider than an area of the bent area BA.Regarding this, FIG. 3 illustrates that a width OW of the opening OP iswider than a width of the bent area BA. The area of the opening OP maybe defined as an area of an opening having a smallest area among theopenings 110 a, 120 a, 130 a, and PVXa respectively of the buffer layer110, the gate insulating layer 120, the inter-insulating layer 130, andthe inorganic protective layer PVX.

The first organic insulating layer 141 may fill the opening OP. Thefirst organic insulating layer 141 is a layer disposed on the inorganicprotective layer PVX. An end portion of the inorganic protective layerPVX may be covered by the first organic insulating layer 141 whilecovering an end portion of the inter-insulating layer 130 in a regionadjacent to the bent area BA.

The first organic insulating layer 141 may be disposed not only in theopening OP of the inorganic insulating layer IL defined in the bent areaBA but also on the data line DL and the first connection metal CM1 inthe display area DA. Due to the opening OP, a level L1 of a portion ofthe first organic insulating layer 141 corresponding to the bent area BAis lower than a level L2 of a portion of the first organic insulatinglayer 141 corresponding to a non-bent area (e.g. the display area DA, ora portion of the first and second areas 1A and 2A in which the inner andouter wirings 210 and 220 are located). Here, it will be understood thata “level of A” represents a “vertical distance/height from the substrate100 to an upper surface of A”.

The first organic insulating layer 141 may contact the substrate 100through the opening OP. The substrate 100 may include a base layer andan inorganic barrier layer. In an exemplary embodiment, as illustratedin FIG. 4A, the substrate 100 may include a first base layer 101, afirst inorganic barrier layer 102, a second base layer 103, and a secondinorganic barrier layer 104 sequentially stacked thereon, for example.In the case where an uppermost layer of the substrate 100 is aninorganic barrier layer, for example, the second inorganic barrier layer104, an opening 104 a corresponding to the bent area BA may be definedin the second inorganic barrier layer 104 and thus the first organicinsulating layer 141 may directly contact the base layer of thesubstrate 100, for example, the second base layer 103.

In an exemplary embodiment, the first and second base layers 101 and 103may include PI, PES, PAR, PEI, PEN, PET, PPS, polyarylate, PC, cellulosetriacetate (“TAC”), CAP, cyclic olefin polymer, and cyclic olefincopolymer, for example.

In an exemplary embodiment, the first and second inorganic barrierlayers 102 and 104 may include a single layer or a multi-layer includingan inorganic material such as SiOx and/or SiNx, for example.

Referring to FIG. 4A, in a region adjacent to the bent area BA, astacked body including the gate insulating layer 120 and theinter-insulating layer 130 may form a step difference with the bufferlayer 110. The inorganic protective layer PVX may cover an upper surfaceof an end portion of the inter-insulating layer 130 adjacent to the bentarea BA, and an end portion of the inorganic protective layer PVX mayextend toward a center of the bent area BA to cover lateral surfaces ofthe gate insulating layer 120 and the inter-insulating layer 130, and anupper surface of the buffer layer 110.

In another exemplary embodiment, referring to FIG. 4B, in a regionadjacent to the bent area BA, a stacked body including the buffer layer110, the gate insulating layer 120, and the inter-insulating layer 130may form a step difference with the second inorganic barrier layer 104.The inorganic protective layer PVX may cover an upper surface of an endportion of the inter-insulating layer 130 adjacent to the bent area BA,and an end portion of the inorganic protective layer PVX may extendtoward a center of the bent area BA to cover lateral surfaces of thebuffer layer 110, the gate insulating layer 120, and theinter-insulating layer 130, and an upper surface of the second inorganicbarrier layer 104.

As illustrated in FIGS. 4A and 4B, in the case where an uppermost layerof the substrate 100 includes the second inorganic barrier layer 104,the inorganic insulating layers IL may collectively denote the secondinorganic barrier layer 104, the buffer layer 110, the gate insulatinglayer 120, the inter-insulating layer 130, and the inorganic protectivelayer PVX.

In a region adjacent to the bent area BA, upper insulating layers (e.g.the second inter-insulating layer, or the first and secondinter-insulating layers) disposed over the inner and outer wirings 210and 220, and lower insulating layers (e.g. the buffer layer and thesecond inorganic barrier layer, or the second inorganic barrier layer)disposed below the inner and outer wirings 210 and 220 may form a stepdifference, and the inorganic protective layer PVX may cover an uppersurface of the lower insulating layer as described above.

In the case where the upper insulating layer and the lower insulatinglayer form a step difference, the lower insulating layer may furtherprotrude toward a center of the bent area BA, and a width OW of theopening OP of the inorganic insulating layer IL in the bent area BA maybe defined by the lower insulating layer. Selectively, an end portion ofthe inorganic protective layer PVX may be disposed on an end portion ofthe lower insulating layer, and thus the width OW of the opening OP ofthe inorganic insulating layer IL may be defined by the lower insulatinglayer and the inorganic protective layer PVX. In an exemplaryembodiment, as illustrated in FIG. 4A, the width OW may be defined bythe openings PVXa, 110 a, and 104 a respectively of the inorganicprotective layer PVX, the buffer layer 110, and the second inorganicbarrier layer 104. In another exemplary embodiment, as illustrated inFIG. 4B, the width OW may be defined by the openings PVXa and 104 arespectively of the inorganic protective layer PVX and the secondinorganic barrier layer 104.

Referring back to FIG. 3, the inner wiring 210 may be electricallyconnected to a pixel in the display area DA. In an exemplary embodiment,the inner wiring 210 may be electrically connected to the first andsecond TFTs T1 and T2, and/or wirings such as the data line DL, and apixel circuit is electrically connected to a display element, forexample. The inner wiring 210 may partially extend to the display areaDA, or may be electrically connected to a conductive layer/wiring (notshown) outside the display area DA.

The outer wiring 220 may be connected, in the non-display area NDA, to awiring (not shown) disposed in a layer different from a layer in whichthe outer wiring 220 is disposed, and/or the terminal unit 20 (refer toFIG. 1) of the non-display area NDA. In an alternative exemplaryembodiment, one end portion of the outer wiring 220 may be exposed tothe outside and connected to an electronic element or the flexible film60, etc., described above with reference to FIG. 1.

The inner wiring 210, which is spaced apart from the outer wiring 220with the bent area BA therebetween, may be electrically connected to theouter wiring 220 through the connection wiring 240 which is a bridgewiring. FIG. 3 illustrates that the conductive layer 230 is disposedbetween the connection wiring 240 and the inner and outer wirings 210and 220, and the conductive layer 230 electrically connects the innerand outer wirings 210 and 220 to the connection wiring 240.

The conductive layer 230 may contact the inner and outer wirings 210 and220 through a first contact hole CNT1 of the inter-insulating layer 130,and the connection wiring 240 may contact the conductive layer 230through a second contact hole CNT2 of the first organic insulating layer141. In this case, a hole PVX-h corresponding to the second contact holeCNT2 may be defined in the inorganic protective layer PVX.

As described above, after the display device is manufactured while thesubstrate 100 is approximately flat, the display device is bent. Adefect such as a crack, or disconnection, etc., in the conductive layer230 may occur during a bending process. To prevent this, the connectionwiring 240 may include a material having relatively high elongation.Also, efficiency in electric signal transfer in the display device maybe improved or a defect occurrence rate during a manufacturing processmay be reduced by forming the inner and outer wirings 210 and 220 of thefirst and second areas 1A and 2A with a material havingelectrical/physical properties different from those of the connectionwiring 240.

In an exemplary embodiment, the inner and outer wirings 210 and 220 mayinclude Mo, and the connection wiring 240 may include Al, for example.The inner and outer wirings 210 and 220 and the connection wiring 240may include a single layer or a multi-layer, for example. In anexemplary embodiment, the connection wiring 240 includes a three-storymulti-layer of Ti/Al/Ti, a thickness of Ti being equal to or less thanabout 0.15 times a thickness of Al, for example, equal to or less thanabout 0.12 times the thickness of Al.

FIG. 3 illustrates a case where the inner and outer wirings 210 and 220are provided during a process of forming the first and second gateelectrodes G1 and G2 and include the same material as that of the firstand second gate electrodes G1 and G2. The conductive layer 230 may beprovided during a process of forming the data line DL and may includethe same material as that of the data line DL. Therefore, the inorganicprotective layer PVX covering the data line DL may also cover theconductive layer 230. The connection wiring 240 may be provided during aprocess of forming the driving voltage line PL, and may include the samematerial as that of the driving voltage line PL.

A protective layer 600A may be disposed on the connection wiring 240.Although the second organic insulating layer 142 and the pixel-defininglayer 150 in the display area DA may extend to the non-display area NDAto form the protective layer 600A covering the connection wiring 240,the invention is not limited thereto. In another exemplary embodiment,the protective layer 600A covering the connection wiring 240 in thenon-display area NDA may include at least one of the second organicinsulating layer 142 and the pixel-defining layer 150, or may beprovided during a separate process (e.g. coating and hardening amaterial in a liquid state or a paste form) by an organic materialdifferent from that of the second organic insulating layer 142 or thepixel-defining layer 150.

FIG. 5 is a cross-section of a display device according to anotherexemplary embodiment and may correspond to cross-sections taken alonglines A-A′ and B-B′ of FIG. 1. Since FIG. 5 illustrates the sameconfiguration as the configuration described with reference to FIG. 3except the arrangement of the inner and outer wirings 210 and 220,differences are mainly described below.

Although FIG. 3 illustrates the inner and outer wirings 210 and 220 aredisposed in a layer in which the first and second gate electrodes G1 andG2 are disposed, for example, on the gate insulating layer 120, theinvention is not limited thereto. In another exemplary embodiment, asillustrated in FIG. 5, the inner and outer wirings 210 and 220 may bedisposed in a layer in which the second storage capacitor plate CE2 ofthe storage capacitor Cst is disposed, for example, on the firstinter-insulating layer 131.

Although FIGS. 3 and 5 illustrate that the inner and outer wirings 210and 220 are disposed in the same layer, the invention is not limitedthereto. In another exemplary embodiment, like the first and second gateelectrodes G1 and G2, one of the inner and outer wirings 210 and 220 maybe disposed on the gate insulating layer 120, and like the secondstorage capacitor plate CE2, the other of the inner and outer wirings210 and 220 may be disposed on the first inter-insulating layer 131.

Though not shown in FIG. 5, characteristics described with reference toFIGS. 4A and 4B are equally applicable to an exemplary embodimentillustrated in FIG. 5.

FIG. 6 is a plan view of a portion of a wiring unit of a display deviceaccording to an exemplary embodiment and may correspond to a portion VIof FIG. 1. FIG. 7 is a cross-sectional view of the wiring unit takenalong line VII-VII′ of FIG. 6, FIG. 8 is a cross-sectional view of thewiring unit taken along line VIII-VIII′ of FIG. 6, and FIG. 9 is across-sectional view of the wiring unit taken along line IX-IX′ of FIG.6.

Referring to FIG. 6, the inner wirings 210 may extend in an X directionand may be spaced apart from each other in a Y direction. Hereinafter,for convenience of description, some of the inner wirings 210 arereferred to as first inner wirings 211 and the rest of the inner wirings210 are referred to as second inner wirings 212.

A contact region of the first inner wiring 211 and the connection wiring240 and a contact region of the second inner wiring 212 and theconnection wiring 240 may be alternately disposed. In an exemplaryembodiment, the contact region of the first inner wiring 211 and theconnection wiring 240 and the contact region of the second inner wiring212 and the connection wiring 240 may be alternately disposed inzigzags, and thus a distance between the first inner wiring 211 and thesecond inner wiring 212 may be reduced and a space efficiency mayimprove, for example.

The first inner wiring 211 and the second inner wiring 212 adjacent toeach other may be disposed on different layers. FIG. 7 illustrates thatthe first inner wiring 211 is disposed on the gate insulating layer 120,and the second inner wiring 212 is disposed on the firstinter-insulating layer 131. Since the first inner wiring 211 and thesecond inner wiring 212 adjacent to each other are disposed in differentlayers with an insulating layer (e.g. the first inter-insulating layer131) therebetween, an unnecessary electric short circuit may beprevented, and an interval between the first inner wiring 211 and thesecond inner wiring 212 may be narrower.

An island type conductive layer 230 is disposed in a contact region ofthe first inner wiring 211 and the connection wiring 240 and a contactregion of the second inner wiring 212 and the connection wiring 240. Theconductive layer 230 is connected to the first or second inner wiring211 or 212 through the first contact hole CNT1, and connected to theconnection wiring 240 through the second contact hole CNT2 as describedabove with reference to FIGS. 3 to 5.

As illustrated in FIG. 8, the connection wiring 240 may be disposed onthe same layer. FIG. 8 illustrates that the connection wiring 240 isdisposed on the first organic insulating layer 141.

Referring to FIGS. 6 and 9, the second inner wiring 212 is connected tothe conductive layer 230 through the first contact hole CNT1 of thesecond inter-insulating layer 132 therebetween, and the connectionwiring 240 is connected to the conductive layer 230 through the secondcontact hole CNT2 of the first organic insulating layer 141therebetween.

The inorganic protective layer PVX may be disposed on the conductivelayer 230 and may continuously cover the first and second inner wirings211 and 212 adjacent to each other except the hole PVX-h overlapping thesecond contact hole CNT2 as illustrated in FIGS. 6 and 9. A firstportion of the inorganic protective layer PVX may directly contact theconductive layer 230, and a second portion of the inorganic protectivelayer PVX may directly contact the second inter-insulating layer 132.

Although the first contact hole CNT1 and the second contact hole CNT2may be offset, the invention is not limited thereto. In anotherexemplary embodiment, at least portions of the first and second contactholes CNT1 and CNT2 may overlap each other.

Although a connection structure of the second inner wiring 212, theconductive layer 230, and the connection wiring 240 has been describedwith reference to FIG. 9 in the above, a connection structure of thefirst inner wiring 211, the conductive layer 230, and the connectionwiring 240 is similar to the structure described with reference to FIG.9 except that the first inner wiring 211 is disposed below the firstinter-insulating layer 131 and a depth of the first contact hole CNT1 isdeeper.

FIG. 10 is a cross-sectional view of a display device according toanother exemplary embodiment, and may correspond to cross-sections takenalong lines A-A′ and B-B′ of FIG. 1. In FIG. 10, same reference numeralsas those in FIG. 3 denote same members, and differences are mainlydescribed below.

Referring to FIG. 10, the inorganic protective layer PVX may cover anupper surface of an end portion of the inter-insulating layer 130adjacent to the bent area BA, and unlike the structure described withreference to FIG. 3, the inorganic protective layer PVX may not cover alateral surface of the inter-insulating layer 130, etc. That is, in aregion adjacent to the bent area BA, an end portion of the inorganicprotective layer PVX may have substantially the same pattern as that ofan end portion of the inter-insulating layer 130.

Since a portion of the first organic insulating layer 141 correspondingto the bent area BA corresponds to the opening OP of the inorganicinsulating layer IL, the level L1 of the portion of the first organicinsulating layer 141 corresponding to the bent area BA is lower than thelevel L2 of the portion of the first organic insulating layer 141corresponding to the non-bent area (e.g. the display area DA, or aportion of the first and second areas 1A and 2A in which the inner andouter wirings 210 and 220 are located) as described above.

FIG. 11A is an enlarged cross-sectional view of a portion of a displaydevice around the bent area of FIG. 10 according to another exemplaryembodiment, and FIG. 11B is a view of a modification of FIG. 11A.

As illustrated in FIGS. 11A and 11B, in the case where an uppermostlayer of the substrate 100 includes the second inorganic barrier layer104, the inorganic insulating layers IL may collectively denote thesecond inorganic barrier layer 104, the buffer layer 110, the gateinsulating layer 120, the inter-insulating layer 130, and the inorganicprotective layer PVX as described above.

Referring to FIG. 11A, in a region adjacent to the bent area BA, astacked body of the gate insulating layer 120 and the inter-insulatinglayer 130 may form a step difference with a stacked body of the bufferlayer 110 and the second inorganic barrier layer 104. Referring to FIG.11B, in the region adjacent to the bent area BA, a stacked body of thebuffer layer 110, the gate insulating layer 120, and theinter-insulating layer 130 may form a step difference with the secondinorganic barrier layer 104.

In the region adjacent to the bent area BA, upper insulating layers(e.g. the second inter-insulating layer or the first and secondinter-insulating layers) disposed over the inner and outer wirings 210and 220 may form a step difference with lower insulating layers (e.g.the buffer layer and the second inorganic barrier layer, or the secondinorganic barrier layer) disposed below the inner and outer wirings 210and 220, and the inorganic protective layer PVX covers an upper surfaceof the upper insulating layers as described above. In the case where theupper insulating layer forms a step difference with the lower insulatinglayer, the lower insulating layer further protrudes toward a center ofthe bent area BA, and thus the width OW of the opening OP of theinorganic insulating layer IL may be defined by the lower insulatinglayer in the bent area BA. In an exemplary embodiment, as illustrated inFIG. 11A, the width OW may be defined by the openings 110 a and 104 arespectively of the buffer layer 110 and the second inorganic barrierlayer 104, for example. In an alternative exemplary embodiment, asillustrated in FIG. 11B, the width OW may be defined by the opening 104a of the second inorganic barrier layer 104.

FIG. 12 is a cross-sectional view of a display device according toanother exemplary embodiment and may correspond to a cross-sectionalview of the display device taken along lines A-A′ and B-B′ of FIG. 1.Since FIG. 12 illustrates the same configuration as the configurationdescribed with reference to FIG. 10 except the arrangement of the innerand outer wirings 210 and 220, differences are mainly described below.

Although FIG. 10 illustrates the inner and outer wirings 210 and 220 aredisposed in a layer in which the first and second gate electrodes G1 andG2 are disposed, for example, on the gate insulating layer 120, theinvention is not limited thereto. In another exemplary embodiment, asillustrated in FIG. 12, the inner and outer wirings 210 and 220 may bedisposed in a layer in which the second storage capacitor plate CE2 ofthe storage capacitor Cst is disposed, for example, on the firstinter-insulating layer 131.

Although FIGS. 10 and 12 illustrate that the inner and outer wirings 210and 220 are disposed in the same layer, the invention is not limitedthereto. In another exemplary embodiment, like the first and second gateelectrodes G1 and G2, one of the inner and outer wirings 210 and 220 maybe disposed on the gate insulating layer 120, and like the secondstorage capacitor plate CE2, the other of the inner and outer wirings210 and 220 may be disposed on the first inter-insulating layer 131.

FIGS. 13A to 13G are cross-sectional views of a method of manufacturinga display device, according to an exemplary embodiment.

FIG. 13A is a cross-sectional view corresponding to first to third maskprocesses.

Referring to FIG. 13A, after forming the buffer layer 110 and thesemiconductor material layer on the substrate 100, the first and secondsemiconductor layers Act1 and Act2 are provided by patterning the bufferlayer 110 and the semiconductor material layer (the first mask process).In an exemplary embodiment, the buffer layer 110 may include SiON, SiOx,and/or SiNx, for example.

After forming the gate insulating layer 120 and the conductive materiallayer, the first and second gate electrodes G1 and G2 are provided inthe display area DA, and the inner and outer wirings 210 and 220 areprovided in the non-display area NDA by patterning the gate insulatinglayer 120 and the conductive material layer (the second mask process).Although FIG. 13A illustrates that the first gate electrode G1 serves asthe first storage capacitor plate CE1, the invention is not limitedthereto as described above.

In an exemplary embodiment, after forming the first and second gateelectrodes G1 and G2, the first and second semiconductor layers Act1 andAct2 may be doped with impurities using the first and second gateelectrodes G1 and G2 as self-align masks. The impurities may be n-typeor p-type impurities. Portions of the first and second semiconductorlayers Act1 and Act2 overlapping the first and second gate electrodes G1and G2 may respectively correspond to the first and second channelregions C1 and C2, and regions respectively at opposite sides of thefirst and second channel regions C1 and C2 doped with impurities mayrespectively correspond to the first and second source regions S1 andS2, and the first and second drain regions D1 and D2.

Next, after forming the first inter-insulating layer 131 and theconductive material layer, the second storage capacitor plate CE2 isprovided in the display area DA by patterning the first inter-insulatinglayer 131 and the conductive material layer (the third mask process).

Although FIG. 13A illustrates that one of the first and second TFTs T1and T2 overlaps the storage capacitor Cst, and thereby the first storagecapacitor plate CE1 of the storage capacitor Cst serves as the firstgate electrode G1, the storage capacitor Cst may not overlap the firstand second TFTs T1 and T2.

FIG. 13B is a cross-sectional view corresponding to a fourth maskprocess.

Referring to FIG. 13B, the second inter-insulating layer 132 is disposedover the substrate 100 on which the third mask process has beenperformed. After that, a first hole 130 h is defined in the display areaDA, and the first contact hole CNT1 is defined in the non-display areaNDA by etching the inter-insulating layer 130. In this case, portions ofthe inter-insulating layer 130 and the gate insulating layer 120corresponding to the bent area BA may be etched and thus the openings130 a and 120 a may be respectively defined in the inter-insulatinglayer 130 and the gate insulating layer 120.

Depending on an etching condition, the buffer layer 110 may not beconsumed as illustrated in an enlarged view of FIG. 13BA, or an upperportion of the buffer layer 110 may be consumed as illustrated in anenlarged view of FIG. 13BB.

FIG. 13C is a cross-sectional view corresponding to a fifth maskprocess.

Referring to FIG. 13C, the conductive material layer is disposed overthe substrate 100 on which the fourth mask process has been performed,and the conductive material layer is patterned (etched). Therefore, thedata line DL and the first connection metal CM1 may be provided in thedisplay area DA, and the conductive layer 230 may be provided in thenon-display area NDA.

Depending on an etching condition, the buffer layer 110 corresponding tothe bent area BA may be consumed. In an exemplary embodiment, asillustrated in an enlarged view FIG. 13CA, an upper portion of thebuffer layer 110 corresponding to the bent area BA may be furtherconsumed, or as illustrated in an enlarged view of FIG. 13CB, a portionof the buffer layer 110 corresponding to the bent area BA may becompletely consumed, for example.

FIGS. 13D and 13E are cross-sectional views corresponding to a sixthmask process.

Referring to FIG. 13D, the inorganic protective layer PVX is disposedover the substrate 100 on which the fifth mask process has beenperformed. In an exemplary embodiment, the inorganic protective layerPVX may include SiON, SiOx, and/or SiNx, for example. In an exemplaryembodiment, the inorganic protective layer PVX may be a layer includingSiNx and having a thickness of about 3000 angstroms (Å), for example.

After that, a photosensitive layer 700 is disposed on the inorganicprotective layer PVX by a halftone mask M. In an exemplary embodiment,the halftone mask M may include a semi-transmissive portion Ma, atransmissive portion Mb, and a light-blocking portion Mc. A firstportion 701 of the photosensitive layer 700 corresponding to thesemi-transmissive portion Ma corresponds to the first connection metalCM1 and a portion of the conductive layer 230. A second portion 702 ofthe photosensitive layer 700 corresponding to the transmissive portionMb corresponds to an opening passing through the photosensitive layer700. A third portion 703 of the photosensitive layer 700 correspondingto the light-blocking portion Mc corresponds to the rest of regionsother than the first and second portions 701 and 702.

After that, the opening PVXa of the inorganic protective layer PVXcorresponding to the bent area BA is provided by etching the inorganicprotective layer PVX exposed through the opening of the photosensitivelayer 700, that is, the second portion 702.

Depending on a condition of an etching process of defining the openingPVXa of the inorganic protective layer PVX, a portion of the lowerinorganic insulating layer(s) disposed below the inorganic protectivelayer PVX may be etched. In an exemplary embodiment, a portion of thebuffer layer 110 corresponding to the opening PVXa may be partiallyremoved as illustrated in an enlarged view of FIG. 13DA. In analternative exemplary embodiment, a portion of the buffer layer 110corresponding to the opening PVXa may be completely removed asillustrated in an enlarged view of FIG. 13DB. In an alternativeexemplary embodiment, at least a portion of the second barrier layer 104corresponding to the opening PVXa may be removed as illustrated in anenlarged view of FIG. 13DC.

Next, referring to FIG. 13E, an opening region 701′ of a photosensitivelayer 700′ is defined by performing ashing and removing a portion of thephotosensitive layer 700 corresponding to the semi-transmissive portionMa. After that, the hole PVX-h of the inorganic protective layer PVX isdefined by etching the inorganic protective layer PVX exposed throughthe opening region 701′. The first connection metal CM1 and theconductive layer 230 below the inorganic protective layer PVX may beexposed through the hole PVX-h.

During an etching process of defining the hole PVX-h of the inorganicprotective layer PVX, a remaining layer of the lower inorganicinsulating layer corresponding to the bent area BA may be completelyremoved. In an exemplary embodiment, the buffer layer 110 and the secondinorganic barrier layer 104 remaining in the bent area BA may becompletely removed as illustrated in an enlarged view of FIG. 13EA, orthe second inorganic barrier layer 104 remaining under the inorganicprotective layer PVX in the bent area BA may be completely removed asillustrated in an enlarged view of FIG. 13EB, for example.

FIG. 13F is a cross-sectional view corresponding to seventh and eighthmask processes.

Referring to FIG. 13F, the first organic insulating layer 141 isprovided by forming the organic material layer over the substrate 100 onwhich the sixth mask process has been performed, and patterning theorganic material layer (the seventh mask process). The first organicinsulating layer 141 is provided as one body such that the first organicinsulating layer 141 is located in the display area DA and thenon-display area NDA, and a hole 141 h exposing the first connectionmetal CM1 and the second contact hole CNT2 exposing the conductive layer230 are defined in the first organic insulating layer 141. In the regionadjacent to the bent area BA, the first organic insulating layer 141covers an end portion of the inorganic protective layer PVX. That is, inthe region adjacent to the bent area BA, the end portion of theinorganic protective layer PVX may cover the inter-insulating layer 130,and simultaneously, may be covered by the first organic insulating layer141.

The level L1 of the portion of the first organic insulating layer 141corresponding to the bent area BA may be less than the level L2 of theother portions of the first organic insulating layer 141 as describedabove. The first organic insulating layer 141 may directly contact thesecond base layer 103 of the substrate 100 as illustrated in enlargedviews of FIGS. 13FA and 13FB.

After that, the driving voltage line PL and the second connection metalCM2 in the display area DA, and the connection wiring 240 in thenon-display area NDA are provided by forming and patterning theconductive material layer (the eighth mask process).

The second connection metal CM2 contacts the first connection metal CM1through the hole 141 h of the first organic insulating layer 141, andthe connection wiring 240 contacts the conductive layer 230 through thesecond contact hole CNT2 of the first organic insulating layer 141.

FIG. 13G is a cross-sectional view corresponding to ninth to eleventhmask processes.

Referring to FIG. 13G, the second organic insulating layer 142 isprovided by forming the organic material layer over the substrate 100 onwhich the eighth mask process has been performed, and patterning theorganic material layer (the ninth mask process). A hole 142 h exposingthe second connection metal CM2 is defined in the second organicinsulating layer 142. The second organic insulating layer 142 may beprovided in not only the display area DA but also the non-display areaNDA.

After that, the pixel electrode 310 is provided by forming an electrodematerial layer on the second organic insulating layer 142 and thepatterning the electrode material layer (the tenth mask process).Although the pixel electrode 310 may be provided by, for example, wetetching, the invention is not limited thereto.

Next, the pixel-defining layer 150 is provided by forming an insulatingmaterial layer on the pixel electrode 310 and patterning the insulatingmaterial layer (the eleventh mask process). An opening exposing thepixel electrode 310 is defined in the pixel-defining layer 150. Thepixel-defining layer 150 may include an organic insulating material.

After that, descriptions of cross-sections corresponding to a process offorming an intermediate layer including an emission layer on the pixelelectrode 310 exposed through the opening of the pixel-defining layer150, and forming an opposite electrode on the intermediate layer, and aprocess of forming an encapsulation layer on the opposite electrode arethe same as the descriptions made with reference to FIG. 3.

Like the mask processes described with reference to FIGS. 13D to 13E inthe above, the lower inorganic insulating layer(s) corresponding to thebent area BA may be completely removed during the process of etching theinorganic protective layer PVX. Therefore, since a mask for removing aremaining layer of the lower inorganic insulating layer(s) correspondingto the bent area BA is not additionally desired, process efficiency mayimprove. Also, since a halftone mask is used, even when a thickness ofthe lower inorganic insulating layer(s) corresponding to the bent areaBA is greater than a thickness of the inorganic protective layer PVX,the hole PVX-h of the inorganic protective layer PVX may be definedwithout damage of the first connection metal CM1, and simultaneously,portions of the lower inorganic insulating layer(s) corresponding to thebent area BA may be completely removed.

FIG. 13D describes the case where the width W1 (refer to FIG. 13D) ofthe second portion 702 of the photosensitive layer 700 corresponding tothe bent area BA is less than the width W2 (refer to FIG. 13D) of theopening 130 a of the inter-insulating layer 130 corresponding to thebent area BA. Therefore, although the inorganic protective layer PVX inthe bent area BA is described to contribute to defining the width OW ofthe opening OP as illustrated in FIG. 13F, the invention is not limitedthereto.

FIG. 14 is a cross-sectional view of the sixth mask process of a methodof manufacturing a display device, according to another exemplaryembodiment.

Referring to FIG. 14, the opening of a photosensitive layer 1700corresponding to the bent area BA, that is, a width W1′ of a secondportion 1702 may be provided to be greater than a width W2′ of theopening 130 a of the inter-insulating layer 130 corresponding to thebent area BA.

In this case, an end portion of the patterned inorganic protective layerPVX may have substantially the same pattern as that of an end portion ofthe inter-insulating layer 130 as illustrated in FIG. 10. Since aspecific method of the mask process illustrated in FIG. 14 andsubsequent processes are the same as those described with reference toFIGS. 13F to 13G, and a structure corresponding thereto is the same asthat described with reference to FIG. 10, descriptions thereof areomitted.

Although the invention has been described with reference to theexemplary embodiments illustrated in the drawings, this is merelyprovided as an example and it will be understood by those of ordinaryskill in the art that various changes in form and details andequivalents thereof may be made therein without departing from thespirit and scope of the invention as defined by the following claims.

What is claimed is:
 1. A display device comprising: a substrateincluding a first area, a second area, and a bent area between the firstand second areas, wherein the substrate is bent; a transistor in thefirst area; a display element electrically coupled to the transistor; aninner wiring in the first area; an outer wiring in the second area; aconnection wiring across the bent area of the substrate and electricallycoupling the inner wiring to the outer wiring; a buffer layer on thesubstrate, a portion of the buffer layer being between the substrate andthe transistor, and the buffer layer having a first opening in the bentarea; an inorganic insulating layer on the buffer layer, the inorganicinsulating layer having a second opening in the bent area; and aninorganic protective layer on the inorganic insulating layer, wherein awidth of the second opening is greater than a width of the first openingsuch that the buffer layer has a step around the first opening.
 2. Thedisplay device of claim 1, wherein an upper surface of the step iscovered by a portion of the inorganic protective layer.
 3. The displaydevice of claim 1, wherein the buffer layer comprises an inorganicinsulating material.
 4. The display device of claim 1, wherein anotherportion of the inorganic protective layer overlaps a portion of at leastone selected from the inner wiring and the outer wiring.
 5. The displaydevice of claim 1, further comprising: a first organic insulating layer,a portion of the first organic insulating layer being in the first andsecond openings and at least partially filing the first and secondopenings.
 6. The display device of claim 5, wherein another portion ofthe first organic insulating layer is interposed between the transistorand the display element.
 7. The display device of claim 5, wherein: theconnection wiring is on the first organic insulating layer, and theconnecting wiring is electrically connected to the inner wiring and theouter wiring through contact holes in the first organic insulatinglayer.
 8. The display device of claim 1, wherein the inorganicprotective layer has an opening overlapping the first opening and thesecond opening.
 9. A display device comprising: a substrate including afirst area, a second area, and a bent area between the first and secondareas, wherein the substrate is bent; a transistor in the first area; adisplay element electrically coupled to the transistor; a buffer layeron the substrate, a portion of the buffer layer being between thesubstrate and the transistor, and the buffer layer having a firstopening in the bent area; an inorganic insulating layer on the bufferlayer, the inorganic insulating layer having a second opening in thebent area; and an inorganic protective layer on the inorganic insulatinglayer, wherein a width of the second opening is greater than a width ofthe first opening, and wherein the buffer layer has a step that isaround the first opening, and an upper surface of the step is covered bya portion of the inorganic protective layer.
 10. The display device ofclaim 9, wherein the buffer layer comprises an inorganic insulatingmaterial.
 11. The display device of claim 1, further comprising: a firstorganic insulating layer, a portion of the first organic insulatinglayer being in the first and second openings and at least partiallyfiling the first and second openings.
 12. The display device of claim11, wherein another portion of the first organic insulating layer isinterposed between the transistor and the display element.
 13. Thedisplay device of claim 9, further comprising: an inner wiring in thefirst area; an outer wiring in the second area; and a connection wiringacross the bent area of the substrate and electrically coupling theinner wiring to the outer wiring.
 14. The display device of claim 13,wherein another portion of the inorganic protective layer overlaps aportion of at least one selected from the inner wiring and the outerwiring.
 15. The display device of claim 13, further comprising: aconductive layer between the connection wiring and one of the innerwiring and the outer wiring.
 16. The display device of claim 15,wherein: the conductive layer is electrically connected to one of theinner wiring and the outer wiring through a first contact hole in theinorganic insulating layer, and a contact region between the one of theinner wiring and the outer wiring and the conductive layer is covered bythe inorganic protective layer.